In video applications, a timing signal can be transferred between two video processing circuits with each video processing circuit having a system clock with a different frequency. For example, a timing signal can be transferred between a pre-stage circuit (in a first video processing circuit) to a post-stage circuit (in a second video processing circuit. Because the phases of the system clocks in the video signal processing circuits are different from each other, the timing signal that is synchronous with the system clock in the pre-stage circuit always jitters in the post-stage circuit when the timing signal remains in a state at the time of being transferred.
Therefore, when a video signal is processed in the post-stage circuit using the jittering timing signal as a reference signal, a horizontal synchronous signal and a vertical synchronous signal in the video signal can become unstable and a distortion of a picture on a screen obtained by the video signal may occur.
For that reason, when a timing signal is transferred between two video signal processing circuits having different system clock frequencies, a PLL (phase locked loop) circuit corresponding to each of the system clocks is assembled in each of the pre-stage circuit and the post-stage circuit in order to obtain a stable timing signal in each of the pre-stage circuit and post-stage circuit to prevent picture distortions on the screen.
Japanese Patent Application Laid-open No. Hei 5-327684 (JPA 5-327684) discloses a timing circuit in which a PLL circuit is disposed in each of the circuits with differing system clock frequencies in order to ensure a proper transfer of a timing signal.
Also, in order to protect an unstable synchronous signal, Japanese Patent Application Laid-open No. Hei 01-144738 (JPA 01-144738) discloses a window method synchronization protecting circuit. In this case, a detection temporal window is set to absorb jitter within a period of the detection window.
However, the above-mentioned timing circuit and window method synchronization can include the following problems.
For example, in the timing circuit disclosed in JPA 5-327648, overall circuit area can become large because a PLL circuit is assembled in each of the circuits having a different system clock frequency. This can increase production costs.
Also, in the window method synchronization circuit disclosed in JPA 01-144738, when a timing signal is set at the upper portion or the lower portion of the screen, AFC (automatic frequency control) is unstable on an upper portion of a screen due to a video signal in the pre-stage circuit and a large jitter may occur on the lower portion of the screen for changing over a head when, for example, the pre-stage circuit is a VTR (video tape recorder). Thus, it can be difficult to stably transfer the timing signal even by the window method synchronization protecting circuit.
In view of the above discussion, it would be desirable to provide a timing signal transferring circuit in which a timing signal may be suitably transferred from a pre-stage circuit to a post-stage circuit of two video signal processing circuits having differing system clock frequencies with reduced distortions of a picture on a screen.